Quantum Capacitance in Scaled-Down III-V FETs

We have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices, the quantum capacitance significantly lowers the overall gate capacitance. In addition, the channel centroid capacitance is also found to have a significant impact on gate capacitance. Our model provides a number of suggestions for capacitance scaling in future III-V FETs. Introduction As Si CMOS approaches the end of the roadmap, finding a new transistor technology that allows the extension of Moore’s law has become a technical problem of great significance. Among the various candidates, III-V-based Field-Effect Transistors represent a very promising technology. In particular, low-effective mass materials with high electron velocities, such as InGaAs and InAs are of great interest [1,2]. A concern with this approach is the relatively small inversion-layer capacitance that is associated with the channel and the limits that this imposes on the gate capacitance that can be attained from barrier thickness scaling [3]. This can seriously limit the current driving ability of scaled down devices. The inversion-layer capacitance has two main contributions: quantum capacitance [4] and centroid capacitance [5]. The first one originates in the penetration of the Fermi level inside the 2D subbands of a quantum well due to the finite density of states. The second one is related to the shape of the charge distribution in the inversion layer. In low effective mass III-V channels, both capacitances can be relatively small. In order to understand the scaling potential of III-V FETs, we have built a physical gate capacitance model and compared it with experimental measurements on InGaAsand InAs-channel HEMTs. From this analysis, we conclude that the relatively small quantum capacitance of InAs-rich channels significantly limits the overall gate capacitance in scaled down designs. In addition, our experiments suggest a large increase of the in-plane effective mass in very thin channel designs as a result of non-parabolicity and strain. This should help to achieve a relatively high electron concentration in future scaled down high-k dielectric III-V FETs. ins C inv C G C 1 Q C 2 Q C 3 Q C 1 cent C 2 cent C 3 cent C ... in s C 1st Subband 2nd Subband 3rd Subband 1 inv C 2 inv C 3 inv C Fig 1. Equivalent circuit diagram of gate capacitance in a III-V FET